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I wrote a quick debouncer code in VHDL that I thought people could enjoy and may be useful for FPGA projects. For more info on debouncers see this post.

As shown in the block diagram below, it takes as inputs a switch signal (SW_IN) and a clock signal (CLK) and outputs a signal SIG.

When SW_IN goes high, the module outputs a once-clock-cycle wide pulse on the next clock rising edge. Then it waits for 8388607 clock cycles (~ 0.17 s when clocked @ 50MHz). This is illustrated in the state transition diagram below.

You can download the code here.

Ever since I discovered the wonders of FPGA boards I wanted to have one of my own (instead of using the one provided by the university only for university projects). Not long ago my wish granted.

Thanks to a very very (extremely) kind professor (I think he prefers to remain anonymous), I got a Spartan D2E FPGA board complete with a DIO1 board. I am thankful for my professor’s generosity and I will never be able to thank him enough.

Have a look at some pictures of the board.

The D2E board

The DIO1 board

I shall be back soon with something implemented on it.