Comments on: Speech Recognition Using FPGA Technology

By: help Voice recognition using VHDL (Altera)

help Voice recognition using VHDL (Altera) — Mon, 26 Sep 2011 02:13:56 +0000

[...] a security switch that will be applied to door locks. given two (2) commands (e.g. open;close). Speech Recognition Using FPGA Technology | Carlitos' Contraptions If its just 2 commands ….. Why do you need voice recognition ? Reply With Quote [...]

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By: emker

emker — Thu, 11 Aug 2011 06:27:01 +0000

Hello Mr. Carlos,
Are you really sampling the sound at 5 KHz?
At 5 KHz you can have the highest frequency of 2500 Hz.
Isn’t it too low? (The second formant can come up to 3500 Hz, and the fifth formant can come up to 5000 Hz. If you save only low part of spectrum, below 2500, the voice sounds become hardly distinguishable.)

By: stepheny

stepheny — Sun, 22 May 2011 02:12:21 +0000

Hi Mr Carlos..
When I run the train.m file, it shows:

??? Index exceeds matrix dimensions.
Error in ==> train at 99
s = xq(ptr:int32(ptr+l*sf/F)); % Store the detected sound in ‘s’.

Can u please explain the mistake that I made?
Thanx in advance ..
Best Regards

By: badro

badro — Sat, 23 Apr 2011 19:26:24 +0000

hi Mr carlos,
please can you explain me what mean master block and slave block
best regards.

By: fester

fester — Tue, 01 Feb 2011 09:29:03 +0000

hi carlitos,

i need some help regarding this project.i will come straight to the point.
its the sound fetcher module,what are the 2 enables ENABLE_shiftreg and ENABLE_8bitFF
used for?bcoz i had gone through quartushelp and i found out that for the D_FFs if omitted
the clock_enable input is default to 1.
one more question,the aim of the downsampler is to sample the data down from 48 to 5Khz
so i jst made the pulse10000 to act like a 5Khz clock and directly fed it to the clock of the downsampler D_FF.
(i put both the enables of the quantizer and downsampler to ’1′ or high.and the enable of the shift_reg to be enabled for the 1st 23 bits on the BCLK for the left channel of the ADCLRCK )
am i thinking wrong,i do not need any code,i jst want ur advice.any help will be greatly appreciated.
(i am using a DE2 board)

thanking you,
fester.

By: kaz

kaz — Sat, 13 Nov 2010 19:10:32 +0000

is it possible for me to view someone who has done the verilog coding for this project ?
thank you

By: VIkas Billa

VIkas Billa — Tue, 09 Nov 2010 11:46:48 +0000

Hello sir

I did this project as my mini poject in M.Tech.

Duration:Jan to May 2010…

I tried this project on DE2 Board.It was partically executed.

The problems are

1.FFT code is not synthesized.
2.FIngerprint is continously changing.

We showed our project to NXP Representative he had appricipated us.

I will send u the code if u send me ur mail id

i wanna work on it.

Regards
Vikas Billa
Harini Nellutla

By: Quick Facts

Quick Facts — Fri, 29 Oct 2010 22:35:26 +0000

Best you should make changes to the webpage title Speech Recognition Using FPGA Technology | Carlitos’ Contraptions to more specific for your subject you make. I loved the blog post nevertheless.

By: enthu

enthu — Sat, 16 Oct 2010 06:52:52 +0000

Can you please explain me the reason for your selection of Altera DE2 board among the numerous boards(eg vertex) available in market?

By: rushil

rushil — Sun, 18 Apr 2010 14:59:34 +0000

Hi,
Your project is good.But I didn’t understand the need of using FFT. Why was FFT used?
Can’t we recognize speech without using FFT? What will be the effect of not using FFT?

By: Carlitos

Carlitos — Sat, 27 Mar 2010 02:29:02 +0000

@Thiru I suggest you make sure you understand the algorithm in general. then, the implementation should be straight forward. It is very important to understand all the basic concepts before you worry about the details of the algorithm.

By: Thiru

Thiru — Fri, 26 Mar 2010 13:47:26 +0000

could u please…reply sir

By: Thiru

Thiru — Sun, 21 Mar 2010 13:59:58 +0000

hai,sir
i’m from india..i already posted a comment..but i didn’t mentioned clearly about my doubts.

i can understand the matlab programs..and i gave one wave file as input & i got the output as distance 0,word is recognized!…

could u please guide me…wat can i do next sir…then after this i have to move to Quartus ii or else here itself steps are there sir…

then sir with the help your documents…i sucessfully created Block design files for memory controller,distance module and mux….

so please guide sir…wat are all steps i can do next…for your Kind Attention my
email:th71comniq@gmail.com

By: Thiru

Thiru — Sun, 21 Mar 2010 13:18:35 +0000

hi carlitos,
I read your project….i like it…and myself i want do the same as my final year project…

i can understand the matlab codes…i ‘m new to Matlab and Quartus II …

could u explain the steps from Matlab to QuartusII…

By: Carlitos

Carlitos — Sat, 20 Mar 2010 01:09:33 +0000

@vasun Speech recognition performed in hardware is different from the software counterpart in the sense that it can be integrated in a single chip and work without a computer. Also, this project aim was mainly combine various disciplines learned in the electrical engineering curriculum in a single capstone project.

By: vasun

vasun — Fri, 19 Mar 2010 12:51:30 +0000

hi carlos,
speech recognition already present in operating sysems like vista.what is the importance of this project.because it hardware cost more.please clear my doubt……..
i also done vhdl code for this project.please reply……

By: jaswar

jaswar — Fri, 12 Mar 2010 17:49:47 +0000

Hi carlos,
the sound length is exactly 1.024 sec or grater than that for input to training phase of speech recognition using matlab.i gave the input using microphone of wavelength 9 sec.after running the program it gives the error INDEX EXCEEDS MATRIX DlMENSION.

By: Asmae

Asmae — Tue, 09 Mar 2010 12:11:33 +0000

hi carlos,
I read your report of your project on speech recognition.
I would like if possible for me to understand the working principle of inputs / outputs of the block Memory Batch operator, and especially “start_addr”, “end_addr” and “done”.
thank you.

By: Carlitos

Carlitos — Tue, 09 Mar 2010 03:44:19 +0000

@Rushil The recognition is only accurate with the same user saying the same word in the same situation.

By: Carlitos

Carlitos — Tue, 09 Mar 2010 03:43:16 +0000

@Rushil The threshold must be calibrated to your particular setup.

By: Rushil

Rushil — Sat, 06 Mar 2010 21:47:49 +0000

Hi,
Considery that one person trains the kit.So, FFT values of his speech will be stored in training mode.Now if during recognition speaker is a different person, then what will be the accuracy of recognition?

By: Rushil

Rushil — Sat, 06 Mar 2010 21:43:23 +0000

Hi,
I have read your project, it is good.I just wanted to know that threshold value remains 0.05 only when you implemented it in fpga or it changes.

By: Asma

Asma — Mon, 01 Mar 2010 20:39:29 +0000

By: HARINI NELLUTLA

HARINI NELLUTLA — Sun, 28 Feb 2010 07:43:39 +0000

I Just want the brief idea about the performance of speech recognition process using VHDL implementation.

By: sujith

sujith — Tue, 23 Feb 2010 12:51:28 +0000

Hello Carlos,
Wats the major advantage in processing Speech in FPGA rather DSP ?
Which compiler u gonna implement here in your project?